Architect Labs used AI to design the Redwood inference chip in under two weeks. The system handled the full flow from spec to FPGA deployment without human intervention. Redwood ran on an FPGA but has not yet been fabricated in silicon. Its projected edge over Nvidia relies on unbuilt Samsung 8nm silicon. The design achieved 95% code and functional coverage without human verification. No bugs were found in the first RTL design sent to the FPGA. Optimization runs on the FPGA dropped from 15 hours to 15-30 minutes. The system explored a microarchitectural search space far larger than human teams. Redwood Nano on FPGA delivered 12.1 tokens/sec on Qwen3 0.6B at 250 MHz. Projected silicon performance is 49 tokens/sec at half the power of Jetson Orin Nano. The team plans to tape out Redwood at TSMC next. They demonstrated recursive self-improvement by using Qwen3 on Redwood to optimize its own operations.
What changed
Chip design cycles typically span years with frozen stages and ad hoc changes.
What it unlocks
Iterating chip designs around fast-changing AI workloads in weeks instead of years.
- <2 weeks for full chip design
- 12.1 tokens/sec on FPGA at 250 MHz
- 49 tokens/sec projected on Samsung 8nm
- 3.4X better performance per watt
What you need to act on it
- AI system access
- written chip specification
Sources